Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1996-12-03
1999-04-27
Martin-Wallace, Valencia
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257336, 257337, 257338, 257344, H01L 2976, H01L 2994
Patent
active
058982027
ABSTRACT:
A semiconductor manufacturing process comprising providing a semiconductor substrate, forming a gate dielectric on an upper surface of the semiconductor substrate, forming a conductive gate on an upper surface of the gate dielectric, forming a first pair of spacer structures on the first and second sidewalls of the conductive gate, introducing a first source impurity distribution into the semiconductor substrate, forming a second pair of spacer structures on respective exterior sidewalls on the first pair of spacer structures, and introducing a drain impurity distribution into the detached drain region of the semiconductor substrate. The semiconductor substrate includes a channel region laterally displaced between a first source region and a detached drain region. The conductive gate includes a first and a second sidewall. Exterior sidewalls of the first pair of spacer structures are displaced from the first and second sidewalls of the conductive gate by a source displacement. A channel boundary of the first source region is laterally displaced from the second sidewall of the conductive gate by the source displacement. Exterior sidewalls of the second pair of spacer structures are laterally displaced from the first and second sidewalls of the conductive gate by a drain displacement. A channel boundary of the detached drain region is laterally displaced from the first sidewall of the conductive gate by the drain displacement. The conductive gate may comprise heavily doped CVD polysilicon or, alternatively, the conductive gate may be formed from a metal such as aluminum, copper, tungsten, or alloys thereof.
REFERENCES:
patent: 4222062 (1980-09-01), Trotter et al.
patent: 4835112 (1989-05-01), Pfiester et al.
patent: 5286664 (1994-02-01), Horiuchi
patent: 5341003 (1994-08-01), Obinata
patent: 5369297 (1994-11-01), Kusunoki et al.
patent: 5516707 (1996-05-01), Loh et al.
patent: 5576556 (1996-11-01), Tamemura et al.
patent: 5696019 (1997-12-01), Chang
patent: 5705439 (1998-01-01), Chang
Streetman, Ben G., Solid State Electronic Devices, Second Edition, 1980 by Prentice-Hall, Inc., pp. 319-321.
Streetman, Ben G., Solid State Electronic Devices, Prentice-Hall, Inc., 1995, pp. 319-321.
Fulford Jr. H. Jim
Gardner Mark I.
Advanced Micro Devices , Inc.
Daffer Kevin L.
Kowert Robert C.
Martin-Wallace Valencia
LandOfFree
Selective spacer formation for optimized silicon area reduction does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Selective spacer formation for optimized silicon area reduction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective spacer formation for optimized silicon area reduction will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-686892