Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1994-04-04
1995-04-18
Wojciechowicz, Edward
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257314, 257326, 257637, 257640, 257900, H01L 2712
Patent
active
054081157
ABSTRACT:
An EEPROM device capable of operating with a single low-voltage power supply includes a control gate electrode (30) and a select gate electrode (14) overlying separate portions of a channel region (32). Electrical charge is stored in an ONO layer (20) overlying a portion of the channel region (32) and separating the control gate electrode (30) from the channel region (32). The memory device is programmed using source-side injection, where electrons traverse the channel region (32) and are injected into trapping sites (34) located within the silicon nitride layer (24) of the ONO layer (20). To provide the necessary field gradient within the channel region (32), the control gate electrode (30) is spaced apart from the source region (16) by the select gate electrode (14). In either of two embodiments, two layers of polysilicon are used to form the select gate electrode (14) and the control gate electrode (30). The second layer of polysilicon is formed as a sidewall spacer on the first layer of polysilicon. Accordingly, a high-density memory device is achieved.
REFERENCES:
patent: 5020030 (1991-05-01), Huber
patent: 5051793 (1991-09-01), Wang
patent: 5063172 (1991-11-01), Manley
patent: 5130769 (1992-07-01), Kuo et al.
patent: 5225362 (1993-07-01), Bergemont
patent: 5274588 (1993-12-01), Manzur et al.
patent: 5280446 (1994-01-01), Ma et al.
T. Y. Chen et al., "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device", IEEE EDL-8, No. 3, Mar. 1987, pp. 93-95.
A. T. Wu et al., "A Novel High Speed 5-Volt Programming EPROM Structure with Source-Side Injection", IEDM 1986, pp. 584-587.
K. Naruke, et al., "A New Flash-Erase EEPROM Cell with a Sidewall Select-Gate on its Source Side", IEDM 1989, pp. 603-606.
Y. Yamauchi, et al., "A 5V-only Virtual Ground Flash Cell with an Auxiliary Gate for High Density and High Speed Application", IEDM 1991, pp. 319-322. Jan.
Dockrey Jasper W.
Motorola Inc.
Wojciechowicz Edward
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