Memory system for storing information data and state-of-radio-tr

Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address

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G06F 1200

Patent

active

058976680

ABSTRACT:
In a memory system capable of using a common address for reading out a combination of upper-digit data and lower-digit data, there are provided an upper-digit memory element 1 for exclusively storing upper-digit data .alpha.(0,0) - - - .alpha.(i,n-1); a lower-digit memory element 2 for exclusively storing lower-digit data .beta.(0) - - - .beta.(i); and inherent address designating means 3-6 for designating individual inherent addresses ADR-a, ADR-b of the upper-digit memory element 1 and the lower-digit memory element 2 in accordance with first address A(0,0) - - - A(i,n-1) specifying a read or write position, and for designating an inherent address ADR-b of the lower-digit memory element 2 in accordance with second address B(0) - - - B(i) used for reading or writing only the lower-digit memory element 2. When the upper-digit data is stored into the upper-digit memory element 1, the first address A(0,0) - - - A(i,n-1) is designated, while when the lower-digit data is stored into the lower-digit memory element 2, the second address B(0) - - - B(i) is designated, thereby omitting minor arithmetic computations in the storing operation of upper-digit data and lower-digit data to the same address. When the data is read out, the first address A(0,0) - - - A(i,n-1) is designated to read out a combination of upper-digit data .alpha.(0,0) - - - .alpha.(i,n-1) stored in the upper-digit memory element 1 and lower-digit data .beta.(0) - - - .beta.(i) stored in the lower-digit memory element 2.

REFERENCES:
patent: 5036486 (1991-07-01), Noguchi et al.
patent: 5123012 (1992-06-01), Suzuki et al.
patent: 5434857 (1995-07-01), Mori

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