Shallow junction formation using multiple implant sources

Details Shallow junction formation using multiple implant sources Shallow junction formation using multiple implant sources

1997-12-02

1999-04-27

Monin, Jr., Donald L.

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

257344, H01L 2906

Patent

active

058973630

ABSTRACT:
Disclosed is a process for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention comprises, first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. An anneal step follows. The result is a shallow junction with a variable concentration profile gradation of dopant. The junction is suitable for forming source and drain regions in MOS transistors, especially where a contact or interconnect is intended to engage the source and drain regions. The variable concentration profile gradation of dopants helps to maintain proper threshold voltage levels and reduces reverse bias current leakage.

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Shu Qin, Chung Chan, Plasma Immersion Ion Implantation doping experiments for microelectronics, J. Vac. Sci. Technol. B, pp. 962-968, Mar. 1994.

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