Method of manufacturing semiconductor devices

Details Method of manufacturing semiconductor devices Method of manufacturing semiconductor devices

1995-12-13

1997-02-04

Powell, William

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

1566521, 1566561, 15665911, 216 67, 216 72, 437190, 437201, H01L 2100

Patent

active

055994245

ABSTRACT:
On a silicon substrate, a silicon oxide layer, a first platinum layer, a dielectric film and a second platinum layer are formed, and then the second platinum layer and the dielectric film are dry etched, via a resist layer, in a 1-5 Pa low pressure region with a mixed gas of HBr and 0.sub.2 as the etching gas. As soon as the first platinum layer is exposed, the unetched portion of dielectric film is etched off in a 5-50 Pa high pressure region, and then the first platinum layer is dry etched again in the low pressure region to form a capacitor consisting of a top electrode, a capacitance insulation layer and a bottom electrode in a semiconductor integrated circuit chip. Using this manufacturing method prevents the deterioration in definition caused by the use of a thick resist and the operation failure of circuit elements such as transistors due to over etching on the insulation layer.

REFERENCES:
patent: 5094712 (1992-03-01), Becker et al.
patent: 5122477 (1992-06-01), Wolters et al.
patent: 5173437 (1992-12-01), Chi
patent: 5254217 (1993-10-01), Maniar et al.
patent: 5258332 (1993-11-01), Horioka et al.
patent: 5286667 (1994-02-01), Lin et al.
patent: 5439840 (1995-08-01), Jones, Jr. et al.

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