Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Patent
1998-04-23
2000-08-01
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
714718, 714 42, G06F 1110, G11C 2900
Patent
active
060981946
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to checking the integrity of memory contents in computers.
2. Description of Related Art
FIG. 1 shows the parts of a computer that are essential as far as the invention is concerned. At the initial stage, after power switch-on, the contents of the main memory RAM are in an undefined state. The initial loading of a conventional computer takes place so that power switch-on generates an initial signal INIT which makes e.g. a processor CPU jump into a predetermined address. This memory has, in a Read Only Memory ROM, an initial loading program the execution of which comprises loading the basic parts of the operating system (OS) from a predetermined location in a disk drive HD. The OS basic parts thus loaded contain more advanced loading programs, which load parts of the OS not only from the locations predetermined for the HD in the ROM but from elsewhere as well. These more advanced loading programs, in turn, load other software modules etc.
The software modules are not necessarily located at contiguous areas on the disk drive HD. Upon reading from the HD, it is often the case that information located at different areas of the HD must be read in succession. A suggestive guideline value is that it is possible to read approximately 1 MB/s of contiguous areas from a disk drive, but in practice the reading rate is no more than one half of this. To take an example, loading 30 MB of software may take approximately a minute.
In process controlling computers, such as switching exchanges, faults may prove to be very expensive. Particularly hard to solve are software defects. Hardware defects can often be detected by making comparisons to another apparatus, known to be in a proper working order. Software defects cannot usually be detected in this manner as there usually exists no reference software known to be operating properly. In many cases, the further drawback is often encountered that on the basis of the symptoms it is often impossible to quickly deduct whether the fault is in the hardware or in the software. Uncontrolled changes in a specific storage area may result from either one of the reasons. If problems occur, it is important that maintenance can be directed at the correct target as soon as possible.
A threat is constituted by vandals and "hackers". If the option for remote maintenance is incorporated in computers, the danger for misuse consequently increases.
In order to detect memory problems, several different solutions have been developed. Prior art knows a so-called parity bit by means of which it is possible to have an even number of 1-bits in the storage location (or, if desired, an odd number). As is well known, the use of parity does not detect a simultaneous change of state by an even number of bits in a storage location.
Another commonly used tool is a Cyclic Redundancy Check, CRC. The CRC sum is a useful tool in detecting errors in serial mode data, such as in disk drives and data links. Relating to matrix data, the CRC sum is faced with two problems. The first of these is that CRC sums cannot be used to reliably detect defects that occur at such intervals that result from the method of calculating the CRC sum. The second problem is associated with the fact that the CRC sum has to be calculated anew if the contents of just one storage location change.
SUMMARY OF THE INVENTION
Resulting from the above, it is an object of the present invention to develop a method and apparatus by means of which memory problems of computers can be detected and the aforementioned problems solved. On the one hand, the invention is based on a method which, based on experience gathered up to date, is extensive enough to detect all conceivable uncontrolled changes in the memory, and on the other hand, on employing this method in the various operations of the computer.
The method and the system according to the invention first of all have the advantage of reliably detecting memory problems. This in turn leads to the second advantage,
REFERENCES:
patent: 4355390 (1982-10-01), Hellwig et al.
patent: 4433388 (1984-02-01), Oosterbaan
patent: 4691319 (1987-09-01), Bose et al.
patent: 4727544 (1988-02-01), Brunner et al.
patent: 4740968 (1988-04-01), Aichelmann, Jr.
patent: 4843633 (1989-06-01), Menich et al.
patent: 4849978 (1989-07-01), Dishon et al.
patent: 4947396 (1990-08-01), Shin et al.
patent: 5007053 (1991-04-01), Iyer et al.
patent: 5345583 (1994-09-01), Davis
patent: 5359659 (1994-10-01), Rosenthal
patent: 5493649 (1996-02-01), Silvka et al.
patent: 5553238 (1996-09-01), Nelson
Pasanen Kari
Rinne Jarmo
Cady Albert De
Chase Shelly A
Nokia Telecommunications Oy
LandOfFree
Detecting memory problems in computers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Detecting memory problems in computers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Detecting memory problems in computers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-674614