System for completing instruction out-of-order which performs ta

Details System for completing instruction out-of-order which performs ta System for completing instruction out-of-order which performs ta

1998-03-24

2000-08-01

Ellis, Richard L.

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Commitment control or register bypass

712 14, 712 23, G06F 938

Patent

active

060981687

ABSTRACT:
A mechanism structured to check for instruction collisions at the Dispatch Unit rather than the Completion Unit. In processors which issue multiple commands simultaneously, a flag bit is sent to the Completion Unit and attached to the instruction in the queue that follows the other in program order if they both have the same targeted address. When the instructions from position 1 and position 2 of the instruction queue are ready to issue, the Completion Unit checks position 2 for a flag bit. If there is a bit, then the instruction in position 1 is discarded and the instruction in position 2 is written to the target address. If there is no flag bit with the instruction in position 2, the instruction in position 1 is written to the target register. This method eliminates the need to compare all the targeted addresses that are associated with the rename registers. It requires two comparisons instead of a minimum of 15 comparisons.

REFERENCES:
patent: 5761474 (1998-06-01), Lesartre et al.
patent: 5887161 (1999-03-01), Cheong et al.
patent: 5898853 (1999-04-01), Panwar et al.
patent: 5944811 (1999-08-01), Motomura
Popescu, Val et al., The Metaflow Architecture, IEEE Micro, Jun. 1991, pp. 10-13 and 63-73.
Johnson, Mike, Superscalar Microprocessor Design, Prentice Hall, 1991, pp. 19-20.
Sohi, Gurindar, Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers, IEEE Transactions on Computers, Vol. 39, No. 3, Mar. 1990, pp. 349-359.

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