Phase locked loop circuit

Details Phase locked loop circuit Phase locked loop circuit

1997-06-20

2000-08-01

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375371, 331 17, 331 1A, H03D 324

Patent

active

060977779

ABSTRACT:
The present invention is intended to reliably achieve a locked PLL even with a short VFO field to correctly perform subsequent reproduction of information data. A PLL circuit of the present invention is supplied with a composite signal composed of a repetitive signal including a pulse train of a constant duty ratio and a random signal including a pulse train allowing variations in duty ratio, where the two signals are arranged in time series. The circuit is provided with a VCO for generating an output signal having a frequency according to a control signal, a PFC for comparing the repetitive signal with the output signal in terms of phase and frequency to generate a phase frequency error signal, a PC for comparing the random signal with the output signal to generate a phase error signal, and loop filters for extracting predetermined band components of the phase frequency error signal and the phase error signal to generate the control signal. Since a PLL is formed including the phase frequency comparator, which has a wide dynamic range and operates at a single lock point, during reading a VFO, a reliable drawing operation is achieved even with a short VFO without miss lock.

REFERENCES:
patent: 4404530 (1983-09-01), Stryer
patent: 4928075 (1990-05-01), Leis
patent: 4942370 (1990-07-01), Shigemory
patent: 4996596 (1991-02-01), Hirao et al.
patent: 5528198 (1996-06-01), Baba et al.
patent: 5848051 (1998-12-01), Ishizawa et al.

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