Low overhead memory designs for IC terminals

Details Low overhead memory designs for IC terminals Low overhead memory designs for IC terminals

1996-12-19

1998-02-03

Canney, Vincent P.

Excavating

39518306, G06F 1100

Patent

active

057152551

ABSTRACT:
An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external terminal thereof, which signal path includes a memory element (121, 123, 127). The memory element includes the buffer (11, 19, 21) that drives signals to/from the terminal.

REFERENCES:
patent: 5109190 (1992-04-01), Sakashita et al.
patent: 5115191 (1992-05-01), Yoshimori
patent: 5134314 (1992-07-01), Wehrmacher
patent: 5206545 (1993-04-01), Huang
David George, "Use a Reprogrammable Approach to Boundary Scan for FPGAs", EDN Electrical Design News, vol. 38, No. 16, 5 Aug. 1993, pp. 97-100.

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