Method for fabricating conducting lines with a high topography h

Details Method for fabricating conducting lines with a high topography h Method for fabricating conducting lines with a high topography h

1998-12-07

2000-08-01

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

438624, 438636, 438736, 438738, 430 5, H01L 21302

Patent

active

06096653&

ABSTRACT:
A method for forming a metal interconnect structure over a high topography dielectric is disclosed. The method comprises the steps of: depositing a conductive layer over the high topography dielectric layer; depositing a planarized oxide layer over the conducting layer, patterning and etching the planarized oxide layer in accordance with a desired metal interconnect pattern using the conducting layer as an etching stop; using the planarized oxide layer as a hard mask, etching the conducting layer in accordance with the desired metal interconnect pattern imparted onto the planarized oxide layer; and depositing a gap-filling oxide layer over the planarized oxide layer and the high topography dielectric layer.

REFERENCES:
patent: 5264076 (1993-11-01), Cuthbert et al.
patent: 5438006 (1995-08-01), Chang et al.
patent: 5545588 (1996-08-01), Yoo
patent: 5723380 (1998-03-01), Wang
patent: 5885902 (1999-03-01), Blasingame et al.

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