Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Patent
1997-11-26
1999-10-12
Lim, Krisna
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
712207, 712216, G06F 938
Patent
active
059648678
ABSTRACT:
A method is provided for optimizing a program by inserting memory prefetch operations in the program executing in a computer system. The computer system includes a processor and a memory. Latencies of instructions of the program are measured by hardware while the instructions are processed by a pipeline of the processor. Memory prefetch instructions are automatically inserted in the program based on the measured latencies to optimize execution of the program. The latencies measure the time from when a load instructions issues a request for data to the memory until the data are available in the processor. A program optimizer uses the measured latencies to estimate the number of cycles that elapse before data of a memory operation are available.
REFERENCES:
patent: 4590550 (1986-05-01), Eilert et al.
patent: 4821178 (1989-04-01), Levin et al.
patent: 4845615 (1989-07-01), Blasciak
patent: 5103394 (1992-04-01), Blasciak
patent: 5151981 (1992-09-01), Westcott et al.
patent: 5446876 (1995-08-01), Levine et al.
patent: 5450586 (1995-09-01), Kuzara et al.
patent: 5475823 (1995-12-01), Amerson et al.
patent: 5479652 (1995-12-01), Dreyer et al.
patent: 5485574 (1996-01-01), Bolosky et al.
patent: 5493673 (1996-02-01), Rindos et al.
patent: 5524263 (1996-06-01), Griffith et al.
patent: 5528753 (1996-06-01), Fortin
patent: 5537541 (1996-07-01), Wibecan
patent: 5572672 (1996-11-01), Dewitt et al.
patent: 5581482 (1996-12-01), Weidenman et al.
patent: 5651112 (1997-07-01), Matsuno et al.
patent: 5704053 (1997-12-01), Santhanam
patent: 5710912 (1998-01-01), Schlansker et al.
patent: 5715425 (1998-02-01), Goldman et al.
patent: 5734856 (1998-03-01), Wang
patent: 5761468 (1998-06-01), Emberson
Abraham et al., Predicting Load Latencies Using Cache Profiling, HPL-94-110, Nov. 1994, copyright Hewlett-Packard Co.
Anderson et al., Continuous Profiling: Where Have all the Cycles Gone? To be published in The Proceedings of the 16.sup.th ACM Symposium on Operating Systems Principles, copyright 1997 by the Assoc. for Computing Machinery.
Ball et al., Efficient Path Profiling, Published in Proceedings of MICRO-29, Dec. 2-4, 1996, in Paris, France, pp. 46-57. Copyright 1996 IEEE.
Bershad et al., Avoiding Conflict Misses Dynamically in Large Direct-Mapped Caches, Proceedings of the 6.sup.th International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 158-170, Oct. 4-7, 1994.
Cohn et al., Hot Cold Optimization of Large Windows/NT Applications, Proceedings of the 29.sup.th Annual International Symposium on Microarchitecture, pp. 80-89, Dec. 1996. Copyright 1996 IEEE.
Conte et al., Using Branch Handling Hardware to Support Profile-Driven Optimization, Proceedings of the 1994 27.sup.th Annual International Symposium on Microarchitecture, Nov. 30-Dec. 2, 1994, San Jose, Calif.
Conte et al., Accurate and Practical Profile-Driven Compilation Using the Profile Buffer, Proceedings of the 29.sup.th Annual International Symposium on Microarchitecture, pp. 36-45, Dec. 2-4, 1996.
Fisher, J.A., Global Code Generation for Instruction-Level Parallelism: Trace Scheduling-2, Hewlett-Packard Technical Report No. HPL-93-43, Jun., 1993. To be published by Springer-Verlag, London, UK.
Horowitz et al., Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors, Proceedings of the 23.sup.rd Annual International Symposium on Computer Architecture, pp. 260-270, May 22-24, 1996.
Hwu et al., The Superblock: An Effective Technique for VLIW and Superscalar Compilation, Center for Reliable and High-Performance Computing, Univ. of Illinois, Urbana-Champaign, Illinois, 61801.
Romer et al., Dynamic Page Mapping Policies for Cache Conflict Resolution on Standard Hardware, Proceedings of the First Symposium for Operating Systems Design and Implementation, pp. 255-266, 1994.
Romer et al., Reducing TLB and Memory Overhead Using Online Superpage Promotion, Proceedings of the 22.sup.nd Annual International Symposium on Computer Architecture, pp. 176-187, Jun. 1995.
Tullsen et al., Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Proceedings of the 23.sup.rd Annual International Symposium on Computer Architecture, Philadelphia, PA, May, 1996.
Tullsen et al., Simultaneous Multithreading: Maximizing On-Chip Parallelism, Proceedings of the 22.sup.nd Annual International Symposium on Computer Architecture, Santa Margherita Ligure, Italy, Jun. 1995.
Verghese et al., Operating System Support for Improving Data Locality on CC-NUMA Compute Servers, Proceedings of the 7.sup.th International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 279-289, Oct. 1-5, 1996.
Young et al., Improving the Accuracy of Static Branch Prediction Using Branch Correlation, Proceedings of the 6.sup.th International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 232-241, Oct. 4-7, 1994.
Anderson Jennifer-Ann M.
Dean Jeffrey
Hicks James E.
Waldspurger Carl A.
Weihl William E.
Digital Equipment Corporation
Lim Krisna
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