Double-die semiconductor package having a back-bonded die and a

Details Double-die semiconductor package having a back-bonded die and a Double-die semiconductor package having a back-bonded die and a

1989-11-20

1991-04-30

Hille, Rolf

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

357 70, 357 80, 361420, 361421, 174 524, H01L 2316, H01L 3902, H01L 2348, H01L 2944

Patent

active

050123238

ABSTRACT:
A semiconductor package incorporating a pair of semiconductor dice on a single leadframe of the type having a wire-bonding region at each end of a die-attachment region which has both an upper and lower surface. The first of said pair of dice is back bonded to the upper surface of said die-attachment region; the second is face bonded to the lower surface of said die-attachment region. Electrical interconnections between said second die and said leadframe pass through an aperture in the leadframe. The dual-die package can be used to approximately double circuit density in a number of different packages, including a dual inline package (DIP), a small-outline J-lead package (SOJ), a single inline package (SIP), zig-zag inline package (ZIP), and other variations of the single- and double-row inline-lead packages.

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