Process for fabricating dual-gate CMOS having in-situ nitrogen-d

Details Process for fabricating dual-gate CMOS having in-situ nitrogen-d Process for fabricating dual-gate CMOS having in-situ nitrogen-d

1996-01-11

1997-07-29

Trinh, Michael

Fishing, trapping, and vermin destroying

437 40GS, 437 34, 437233, H01L 218238

Patent

active

056521669

ABSTRACT:
A process for fabricating dual-gate CMOS of semiconductor devices having in-situ nitrogen-doped polysilicon by rapid thermal chemical vapor deposition in a rapid thermal reactor is disclosed. The process comprises the steps of first fabricating components of the dual-gate CMOS on a semiconductor silicon substrate. The dual-gate CMOS components includes P- and N-wells and source/drain regions formed in the silicon substrate. Gate oxide for the dual-gate CMOS is then grown. A thin nitrogen-doped polysilicon film is then deposited over the gates, and followed by the deposition of a undoped polysilicon film, which covers over the surface of the thin nitrogen-doped polysilicon film. Ions are then implanted into the dual-gates CMOS. In the process, the thin nitrogen-doped polysilicon film is deposited by introducing SiH.sub.4 and NH.sub.3 gas mixture into the rapid thermal reactor under a pressure of about 0.4 torr at about 750.degree. C. The thin nitrogen-doped polysilicon film has a thickness of about 60 .ANG.. The undoped polysilicon film is formed by deposition of SiH.sub.4 after the NH.sub.3 gas is evacuated from the rapid thermal reactor, and has a thickness of about 2,000 to 3,000 .ANG.. N.sub.2 O, NO and O.sub.2 gases may be utilized in the rapid thermal procedure for the formation of the oxide layer. Once the oxide layer is formed, the process of forming polysilicon may be continued in the reaction chamber without needing to be exposed to the ambient air. Contamination to the device is therefore avoided and the product yield rate improved. The rapid thermal reactor employed in the process is a load-locked single reactor.

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