Patent
1997-01-06
1998-03-31
Sheikh, Ayaz R.
395384, G06F 930
Patent
active
057348545
ABSTRACT:
In a computer where instructions are fetched in segments and where segments of an instruction are assembled before execution is initiated, processing of instructions is accelerated by examining segments of the instructions they are fetched. The information obtained from such examination is then used to shorten the decoding step for the instruction.
REFERENCES:
patent: 3656123 (1972-04-01), Cainevale et al.
patent: 3657705 (1972-04-01), Mekota et al.
patent: 3771138 (1973-11-01), Celtruda et al.
patent: 4236206 (1980-11-01), Strecker et al.
patent: 4325118 (1982-04-01), DeVita et al.
patent: 4346437 (1982-08-01), Blahut et al.
patent: 4363091 (1982-12-01), Pohlman, III et al.
patent: 4454578 (1984-06-01), Matsumoto
patent: 4502111 (1985-02-01), Riffe et al.
patent: 4890218 (1989-12-01), Bram
patent: 5057837 (1991-10-01), Colwell et al.
patent: 5113515 (1992-05-01), Fite et al.
patent: 5117488 (1992-05-01), Noguchi et al.
patent: 5233696 (1993-08-01), Suzuki
patent: 5337415 (1994-08-01), DeLano et al.
patent: 5459844 (1995-10-01), Eickemeyer et al.
patent: 5481751 (1996-01-01), Alpert et al.
patent: 5502826 (1996-03-01), Vassiliadis et al.
Lindauer et al., "Instruction Unit," IBM Technical Disclosure Bulletin, vol. 7, No. 1 (Jun. 1964).
Sheikh Ayaz R.
Wiley David A.
Zilog Inc.
LandOfFree
Fast instruction decoding in a pipeline processor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fast instruction decoding in a pipeline processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fast instruction decoding in a pipeline processor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-61258