Process for forming vias on integrated circuits

Details Process for forming vias on integrated circuits Process for forming vias on integrated circuits

1986-03-24

1987-06-02

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156644, 156646, 156652, 156653, 156656, 156657, 1566591, 156901, 20419235, C23F 102, B44C 122, C03C 1500, C03C 2506

Patent

active

046700919

ABSTRACT:
In a process of forming vias for multilevel interconnects used in integrated circuits, a layer of a first metal is formed on a semiconductor substrate. A layer of a second metal is formed on the first metal layer. The second metal layer is etched in a predetermined via pattern with a second etchant which reacts with the second metal and which is substantially unreactive with the first metal. The first metal layer is then etched with a first etchant which reacts with the first metal and which is substantialy unreactive with the second metal or with the semiconductor substrate in order to form a predetermined contacting relationship with the predetermined via pattern. This process may be used to generate second and subsequent levels of vias and interconnects which can be used to contact metal layer at any level directly to the substrate by building via posts from the substrate to any desired metal layer.

REFERENCES:
patent: 2731333 (1956-01-01), Ko et al.
patent: 3489656 (1970-01-01), Balde
patent: 3679941 (1972-07-01), LaCombe et al.
patent: 3756887 (1973-09-01), Cruthers
patent: 3904461 (1975-09-01), Estep et al.
patent: 4172004 (1979-10-01), Alcorn et al.
patent: 4410622 (1983-10-01), Dalal et al.
IBM Technical Disclosure Bulletin, vol. 19, No. 9, Feb. 1977, pp. 3364-3365, New York, US; W. C. Metzger et al.: "Forming Planar Integrated Circuit Metallization".
Journal of the Electromechanical Society, vol. 131, No. 1, Jan. 1984, pp. 115-120, Manchester, US; C. C. Tang et al.: "Tungsten Etching in CF4 and SF6 Discharges".
"A Novel Planar Multilevel Interconnection Technology Utilizing Polyimide" by Sato et al, vol. PHP-9, No. 3, 9/73, pp. 176-180. IEEE Transactions on Parts, Hybrids, and Packaging.
"Pillars--The Way to Two Micron Pitch Multilevel Metallization" by Oakley et al, June 21-22, 1984, V-MIC Conference, pp. 23-29.

Affiliated with

Also associated with

Rating

Process for forming vias on integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for forming vias on integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for forming vias on integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-611203