Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1992-08-17
1995-10-17
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
36523003, G11C 700
Patent
active
054596904
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated semiconductor memory with a redundancy arrangement.
In modern integrated semiconductor memories, the memory cells are disposed in a plurality of memory field block units of one to several memory field blocks. In operation, for the sake of saving current and time, only one memory field block unit is activated at a time, as a function of address signals. To increase the yield in manufacturing these semiconductor memories, it has long been known to provide so-called redundant word lines with redundant memory cells along the redundant word lines. Memories with a plurality of memory field block units accordingly have a further one to 8 or 16 redundant word lines with redundant memory cells in the memory field block units, in addition to the normal word lines with normal memory cells. In case of need, in other words if redundant memory cells are intended to replace defective normal memory cells ("redundancy situation"), the redundant word lines are triggered instead of the normal word lines. As is known, this is done via so-called redundancy decoders, which are programmable to the address of the applicable normal word line with the defective memory cells to be replaced (the programming is to be done via so-called fuses, which can be interrupted by means of electric current or a laser beam).
To increase the effectiveness of such redundancy provisions, various redundancy architectures are presented in an article entitled "A Flexible Redundancy Technique for High Density DRAM's" IEEE Journal of Solid-State Circuits, Vol. 26, No. 1, January 1991, pp. 12-17. A common feature of all the architectures is that in each individual memory field block unit, only a maximum of as many normal word lines as corresponds to the number of redundant word lines of such a memory field block unit can be replaced with redundant word lines. In practice, this can mean that a semiconductor memory of this kind may contain more normal word lines with defective memory cells in a memory field block unit than there are redundant word lines, with corresponding redundant memory cells, in the same memory field block unit. Such a memory is then "unrepairable" with the aid of the redundant architectures known thus far, even though there may still be enough redundant word lines with redundant memory cells in other memory field block units than the memory field block unit in question, and those redundant word lines and memory cells in these other memory field block units would then not be utilized.
The object of the present invention is to create an integrated semiconductor memory with a redundancy arrangement that as needed, in other words in the presence of normal word lines with defective memory cells, enables better utilization of the redundancy arrangement.
SUMMARY OF THE INVENTION
This object is attained, in a generic semiconductor memory, with at least one programmable redundant block decoder for selection of the redundant word line decoders, both in cases in which a redundant word line to be selected, having replacement redundant memory cells, is located in the same memory field block unit as the normal line having the memory cells to be replaced, and in cases in which a redundant word line to be selected, having replacement redundant memory cells, is disposed in an arbitrary different memory field block unit from the normal word line having the memory cells to be replaced. Advantageous embodiments and further features are recited in the dependent claims.
The invention will now be described in further detail, in conjunction with the drawing. Shown are:
BRIEF DESCRIPTION OF DRAWINGS
FIGS. 1-5, various embodiments of the invention in general;
FIGS. 6-13, advantageous details of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIGS. 1-5, in highly schematic form, show various embodiments of the semiconductor memory according to the invention, including some circuit parts that are already known, which although not directly involved in the
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Rieger Johann
Stecker Johann
Greenberg Laurence A.
Lerner Herbert L.
Popek Joseph A.
Siemens Aktiengesellschaft
Zarabian A.
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