Driver for interfacing integrated circuits to transmission lines

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction

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326 30, 326 86, H03K 1716

Patent

active

056442521

ABSTRACT:
In order to effectively interface a plurality of integrated circuits to a bus, an improved driver is disclosed. The driver includes an inverter provided between a power source and a ground level, and an output transistor whose gate is coupled to an output of the inverter and whose source-drain path is coupled between an output of the driver and the second power source. A feedback path is coupled between the output of the driver and the output of the inverter. The feedback path includes first and second transistors coupled in series. The first transistor has its gate coupled to an input of the inverter, while the second transistor has its gate coupled to the output of the inverter via delay means. The driver is characterized by an impedance controller which is provided between the output of the inverter and the second power source. The impedance controller stepwisely adjusts impedance of the output transistor when an input signal to the inverter changes from a low logic level to a high logic level. As an alternative to or in combination of the impedance controller, another impedance controller is provided which is provided in parallel with the second transistor and which stepwisely adjusts the impedance of the output transistor when the input signal to the inverter changes from the low logic level to the high logic level.

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"High Speed CMOS Off-Chip Driver Designs for Improved Performance", IBM Technical Dislcosure Bulletin, vol. 31, No. 5, Oct. 1988, pp. 331-332.

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