Method and apparatus for position independent reconfiguration in

Electrical computers and digital processing systems: memory – Address formation – Address mapping

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

711202, 711204, 712 16, 712 23, G06F 1208, G06F 1340

Patent

active

061087602

ABSTRACT:
A method and an apparatus for position independent reconfiguration in a network of multiple context processing elements are provided. Wach multiple context processing element in a networked array of multiple context processing elements has an assigned physical identification. Virtual identifications may also be assigned to a number of the multiple context processing elements. Data is transmitted to at least one of the multiple context processing elements of the array, the data comprising control data, configuration data, an address mask, and a destination identification. The transmitted address mask is applied to either the physical or virtual identification and to a destination identification. The masked physical or virtual identification is compared to the masked destination identification. When the masked physical or virtual identification of a multiple context processing element matches the masked destination identification, at least one of the number of multiple context processing elements are manipulated in response to the transmitted data. Manipulation comprises programming a multiple context processing element with at least one configuration memory context and selecting a configuration memory context to control the functioning of the multiple context processing element.

REFERENCES:
patent: 4597041 (1986-06-01), Guyer et al.
patent: 4748585 (1988-05-01), Chiarulli et al.
patent: 4754412 (1988-06-01), Deering
patent: 4858113 (1989-08-01), Saccardi
patent: 4870302 (1989-09-01), Freeman
patent: 4967340 (1990-10-01), Dawes
patent: 5020059 (1991-05-01), Gorin et al.
patent: 5081575 (1992-01-01), Hiller et al.
patent: 5233539 (1993-08-01), Agrawal et al.
patent: 5301340 (1994-04-01), Cook
patent: 5317209 (1994-05-01), Garverick et al.
patent: 5317755 (1994-05-01), Hartley et al.
patent: 5336950 (1994-08-01), Popli et al.
patent: 5426378 (1995-06-01), Ong
patent: 5457408 (1995-10-01), Leung
patent: 5469003 (1995-11-01), Kean
patent: 5581199 (1996-12-01), Pierce et al.
patent: 5684980 (1997-11-01), Casselman
patent: 5742180 (1998-04-01), DeHon et al.
patent: 5754818 (1998-05-01), Mohamed
patent: 5765209 (1998-06-01), Yetter
patent: 5778439 (1998-07-01), Trimberger et al.
patent: 5880598 (1999-03-01), Duong
patent: 5956518 (1999-09-01), DeHon et al.
Hon, et al; "Reinventing Computing", Mar. 1996; MIT Al Lab; p. 1.
Baker; "Programming Silicon"; Aug. 28, 1995; Electronic Engineering Times; p. 73.
Brown; "Smart Compilers Puncture Code Bloat"; Oct. 9, 1995; Electronic Engineering Times; pp. 38 and 42.
Snyder; "A Taxomony of Synchronous Parallel Machines"; Proceedings of the 1988 Internatinal Conference on Parallel Processing; Aug. 15-19, 1998; pp. 281-285.
Gray, et al.; "Configurable Hardware: A New Paradigm for Computation"; 1989; Massachusetts Institute of Technology; pp. 279-296.
Carter, et al.; "A User Programmable Reconfigurable Logic Array"; IEEE 1986 Custom Integrated Circuits Conference; pp. 233-235.
Valero-Garcia, et al.; "Implementation of Systolic Algorithms Using Pipelined Functional Units"; IEEE Proceedings on the International Conf. on Application Specific Array Processors; Sep. 5-7, 1990; pp. 273-283.
Razdan, et al; "A High-Performance Microarchitecture with Hardware-Programmable Functional Units"; Micro-27 Proceedings of the 27th Annual International Symposium on Microarchitecture Nov. 30-Dec. 2, 1994; pp. 172-180.
Guo, et al.; "A Novel Programmable Interconnect Architecture with Decoded Ram Storage"; Proceedings of the IEEE Custom Integrated Circuits Conference; May 1-4, 1994; pp. 193-196.
Vuillemin, et al.; "Programmable Active Memories: Reconfigurable Systems Come of Age"; IEEE Transactions on VLSI Systems; 1995; pp. 1-15.
Johnson, et al.; "General-Purpose Systolic Arrays"; IEEE Nov. 1993; pp. 20-31.
Clark; "Pilkington preps reconfigurable video DSP"; EE times, week of Jul. 31, 1995.
Fiske, et al.; "The Reconfigurable Arithmetic Processor"; The 15th. Annual International Symposium on Computer Architecture; May 30-Jun. 2, 1988; pp. 30-36.
Beal, et al.; Design of a Processor Element for a High Performance Massively Parallel SIMD System; Int'l Journal of High Speed Computing, vol. 7, No. 3; Sep. 1995; pp. 365-390.
Snyder; "An Inquiry into the Benefits of Multigauge Parallel Computation"; Proceedings of the 1995 International Conference on Parallel Processing; Aug. 20-23, 1995; pp. 488-492.
Wang, et al.; "An Array Architecture for Reconfigurable Datapaths"; "More FPGAs", W.R. Moore & W. Luk; 1994 Abingdon EE&CS Books; pp. 35-46.
Bridges; "The GPA Machine: A Generally Partitionable MSIMD Architecture"; IEEE Third Symposium on The Frontiers of Massively Parallel Computation Feb. 1990; pp. 196-203.
Morton, et al.; "The Dynamically Reconfigurable CAP Array Chip I"; IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986; pp. 820-826.
Alexander, et al.; "A Reconfigurable Approach to a Systolic Sorting Architecture"; IEEE Feb. 1989; pp. 1178-1182.
Blazek, et al. ; "Design of a Reconfigurable Parallel RISC-Machine"; North-Holland Microprocessing and Microprogramming, 1987; pp. 39-46.
Masera, et al.; "A Microprogrammable Parallel Architecture for DSP"; Proceedings of the International Conference on Circuits and Systems, Jun. 1991; pp. 824-827.
Xilinx Advance Product Information; "XC6200 Field Programmable Gate Arrays"; Jan. 9, 1997 (Version 1.8); pp. 1-53.
Sowa, et al.; "Parallel Execution on the Function-Partitioned Processor with Multiple Instruction Streams"; Systems and Computers in Japan, vol. 22, No. 4, 1991; pp. 22-27.
Wang, et al.; "Distributed Instruction Set Computer"; Proceedings of the 1988 International Conference on Parallel Processing; Aug. 15-19, 1988; pp. 426-429.
Mirsky, Ethan A., "Coarse-Grain Reconfigurable Computing," Thesis submitted at the Massachusetts Institute of Technology, Jun. 1996.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for position independent reconfiguration in does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for position independent reconfiguration in, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for position independent reconfiguration in will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-594952

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.