High-speed random access memory device

Details High-speed random access memory device High-speed random access memory device

1999-08-25

2000-08-22

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

365220, 365205, 36523006, G11C 700

Patent

active

061082430

ABSTRACT:
The present invention is an FCRAM comprising a first stage for performing command decoding, a second stage for performing sense amplifier activation, and a third stage for performing data input and output, configured in a pipeline structure, a plurality of data bits being transferred in parallel between the sense amplifiers and the third stage, wherein sense amplifiers are deactivated automatically and a reset operation is performed after data has been transferred in parallel between sense amplifiers and the third stage, in response to a standard read or write command.

REFERENCES:
patent: 5886946 (1999-03-01), Ooishi
patent: 5892730 (1999-04-01), Sato et al.
patent: 5959930 (1999-09-01), Sakurai
patent: 5973991 (1999-10-01), Tsuchida et al.
patent: 5978246 (1999-11-01), Shindo
patent: 6028810 (2000-02-01), Ooishi

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