Semiconductor dynamic random-access memory device

Details Semiconductor dynamic random-access memory device Semiconductor dynamic random-access memory device

1993-02-01

1994-10-04

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Differential sensing

365149, 365203, 365207, 365 51, G11C 700

Patent

active

053532554

ABSTRACT:
A semiconductor memory device having memory cells each comprising a single transistor and a single capacitor. The memory device has two kinds of bit line pairs, a main bit line pair and a sub-bit line pair. Some memory cells are connected to the first main bit line with their capacitor sides and to the second sub-bit line with their transistor sides. Other memory cells are connected to the second main bit line with their capacitor sides and to the first sub-bit line with their transistor sides. A sub-sense amplifier is provided to amplify and transmit the difference voltage of the sub-bit line pair to the main bit line pair. The main bit line pair is connected to a main sense amplifier which amplifies and outputs the difference voltage of the main bit line pair.

REFERENCES:
patent: 4920517 (1990-04-01), Yamauchi et al.
patent: 4926382 (1990-05-01), Sakui et al.

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