Method of manufacturing self-aligned bit-line and device manufac

Details Method of manufacturing self-aligned bit-line and device manufac Method of manufacturing self-aligned bit-line and device manufac

Filed on

1996-07-29

Date issued

1998-03-31

Examiner

Le, Vu A.

Patent Class

Static information storage and retrieval

SubClass

Floating gate

Other Related Categories

257314, 257315, 257316, H01L 2358

Type

Patent

Status

active

Patent number

057346070

Description

ABSTRACT:
An integrated circuit EPROM memory device includes devices to which electrical connections are to be made. A tunnel oxide layer on a semiconductor substrate carries an array of gate stacks with sidewalls with trench spaces therebetween comprising wider drain trench spaces and narrower source trench spaces down to the tunnel oxide layer. Gate stacks include a doped polysilicon floating gate over the tunnel oxide layer, a dielectric layer over the floating gate, a polysilicon control gate over the dielectric layer covered by a silicon dioxide dielectric layer and a silicon nitride layer. Source/drain regions lie between the stacks with alternating source regions and drain regions below the trench spaces between the sidewalls. Spacers are adjacent to the sidewalls of the drain trench spaces. Spacer dielectric plugs fill source trench spaces. A blanket dielectric layer overlies the stacks and the spacer dielectric plugs. Bitlines extend across the stacks into contact with the drain regions through the drain trench spaces. The memory devices include a self-aligned bitline structure formed simultaneously with electrical contacts to the drains.

REFERENCES:
patent: 5204286 (1993-04-01), Doan
patent: 5231051 (1993-07-01), Baldi et al.
patent: 5260894 (1993-11-01), Noda
patent: 5559735 (1996-09-01), Ono et al.
patent: 5641989 (1997-06-01), Tomioka

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