Method and circuit for reducing cell plate noise

Details Method and circuit for reducing cell plate noise Method and circuit for reducing cell plate noise

1997-02-10

1998-03-31

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Capacitors

365206, G11C 1124

Patent

active

057346038

ABSTRACT:
A method and a circuit of reducing cell plate noise induced by memory access are provided. The circuit includes a sample and hold circuit, a differential amplifier and a current source. The sample and hold circuit maintains a sample voltage identical to the normal level of the reference cell plate voltage. The differential amplifier compares the sample voltage with the reference cell plate voltage during memory access in the DRAM and generates a difference voltage corresponding to the cell plate noise. The current source, which is controlled by the difference voltage, can modify the reference cell plate voltage to reduce the cell plate noise during memory access.

REFERENCES:
patent: 4259729 (1981-03-01), Tokushige
patent: 4593382 (1986-06-01), Fujishima et al.
patent: 4769784 (1988-09-01), Doluca et al.
patent: 5255232 (1993-10-01), Foss et al.

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