Semiconductor memory device having circuit for activating predet

Details Semiconductor memory device having circuit for activating predet Semiconductor memory device having circuit for activating predet

1995-03-22

1996-11-12

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Testing

365149, G11C 700

Patent

active

055746918

ABSTRACT:
When a disturb refresh mode is detected by a mode detecting circuit, a row decoder control circuit simultaneously activates every several word lines of a memory cell array of a block selected by an operation block selecting circuit through a row decoder and a driving circuit, reads out data written in a normal mode, and determines a memory cell having a threshold value lower than that of a design value upon determination of match of read data and written data.

REFERENCES:
patent: 4774061 (1988-05-01), Takemae et al.
patent: 4906994 (1990-03-01), Hoffman et al.
patent: 5109382 (1992-04-01), Fukunaka
patent: 5212442 (1993-05-01), O'Toole
patent: 5305267 (1994-04-01), Haraguchi et al.
patent: 5339273 (1994-08-01), Taguchi
patent: 5355342 (1994-10-01), Ueoka

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