Impedance restoration for fast carry propagation

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G05F 750

Patent

active

045368554

ABSTRACT:
An improved circuit for performing high speed arithmetic computations is described, and includes a mechanism for dynamically deleting faulty data bits in a configuration for minimizing propagation delay paths. The invention is particularly applicable to an associative processor wherein the data word length and rate of flow of data may vary from one instruction to the next. In accordance with the invention, data propagation delay time is minimized as is the number of required circuit interconnections, thereby making the invention easily manufacturable on an LSI chip. The advantages of the circuit design are multiplied in an associative processor, since such processors are highly reconfigurable and must be able to exclude unwanted bits from an arithmetic operation, to change data word sizes and to delete failed bits. The present invention is advantageously implemented in arithmetic carry circuits and in cascaded multiplexer logic circuits, which may effectively be implemented in MOS (metal oxide semiconductor) integrated circuits, or in CMOS (complementary MOS) integrated circuits in which a plurality of stages of such circuits must be connected in series, i.e. eight, sixteen, thirty-two, etc., while still providing a rapid execution speed.

REFERENCES:
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patent: 3728532 (1973-04-01), Pryor
patent: 3766371 (1973-10-01), Suzuki
patent: 3925651 (1975-12-01), Miller
patent: 4052604 (1977-10-01), Maitland et al.
patent: 4229803 (1980-10-01), Rhodes
patent: 4357675 (1982-11-01), Freyman
patent: 4504749 (1985-03-01), Yoshida

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