Semiconductor memory circuit in which pattern widths of switchin

Details Semiconductor memory circuit in which pattern widths of switchin Semiconductor memory circuit in which pattern widths of switchin

1998-01-20

2000-07-11

Nelms, David

Static information storage and retrieval

Addressing

Multiple port access

36518905, 36523003, 365240, G11C 800

Patent

active

060882859

ABSTRACT:
A semiconductor memory circuit comprises a memory array including an X decoder and column units. Each of the column units has a Y decoder, memory cells and bit line pairs. The semiconductor memory circuit further comprises switching circuits each having an input connected to one of the Y decoders and outputs. The switching circuit is connected to the input and one of the outputs in response to a control signal. The semiconductor memory circuit further comprises buffers each of which is connected to one of the outputs of the switching circuits, ports each of which is connected to one of the buffers and a memory control signal generating circuit outputting the X address and Y address.

REFERENCES:
patent: 5400292 (1995-03-01), Fukiage et al.
patent: 5680365 (1997-10-01), Blankenship
patent: 5726948 (1998-03-01), Hush et al.
patent: 5732041 (1998-03-01), Joffe
patent: 5835417 (1998-10-01), Ayukawa et al.

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