MOS transistor and fabrication process therefor

Details MOS transistor and fabrication process therefor MOS transistor and fabrication process therefor

1996-08-08

1998-03-31

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257389, 257401, 257406, 257408, 257506, 438 29, 438 42, 438228, H01L 2972, H01L 2973

Patent

active

057341850

ABSTRACT:
An MOS transistor comprises a semiconductor substrate having a field region; a gate electrode formed on the semiconductor substrate through the intermediatry of a gate insulating film; and source/drain regions formed in the semiconductor substrate; wherein the field region including at least a lower insulating film and an upper insulating film made of a material permitting the upper insulating film to be selectively etched with respect to the lower insulating film; the gate electrode being configured such that the gate length of a top surface thereof is greater than the gate length of a bottom surface thereof facing a channel region positioned between the source/drain regions; the gate electrode having a sidewall spacer formed of a sidewall insulating layer made of the lower insulating film and a material permitting the sidewall insulating layer to be selectively etched with respect to the upper insulating film, the sidewall spacer contacting a side wall of the gate electrode for covering an outer periphery of the channel region; and the channel region being substantially leveled with the source/drain regions.

REFERENCES:
patent: 5102816 (1992-04-01), Manukonda et al.
S. Kimura et al, Applied Physics, vol. 61, No. 11 (1992), pp. 1143-1146.

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