Stacked CVD oxide architecture multi-state memory cell for mask

Details Stacked CVD oxide architecture multi-state memory cell for mask Stacked CVD oxide architecture multi-state memory cell for mask

1995-05-31

1996-11-19

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257390, 257392, 257638, 437 56, 437 59, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

055765734

ABSTRACT:
A multi-state memory cell for a mask ROM device. Source/drain regions are arranged on a substrate as strips extending along a first direction on the plane of the substrate and bit lines. Gate oxide layers are arranged on the substrate as strips extending along a second direction. Gate electrodes are each formed on top of each of the gate oxide layers as strips extending along the second direction. The gate oxide layers have a number of selected thickness' arranged in a differential series. Each of the transistor channel regions, together with their corresponding one of the neighboring source/drain pair, the gate oxide layer on top, and the gate electrodes further on top thereof constitute one of the memory cells that can have its threshold voltage varied among the differential series of thicknesses allowing for the storage of a multi-bit equivalent of memory content for the memory cell.

REFERENCES:
patent: 3829888 (1974-08-01), Hashimoto et al.
patent: 3896482 (1975-07-01), Brechling et al.
patent: 4658282 (1987-04-01), Matzen, Jr.
patent: 4866002 (1989-09-01), Shizukuishi et al.
patent: 5455438 (1995-10-01), Hashimoto et al.

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