Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1975-12-12
1978-02-14
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Bad bit
364900, G11C 1300
Patent
active
040742369
ABSTRACT:
A memory device is disclosed which has a memory portion comprising a plurality of major memory blocks, each composed of a plurality of minor memory blocks which, in turn, are respectively composed of a plurality of memory cells. Information as to whether each of the minor memory blocks making up each of the major memory blocks includes defective memory cells or not is registered and when an address corresponding to any one of the major memory blocks is selected, a predetermined number of minor memory blocks including no defective memory cells are selected with reference to the registered information and data is input to the selected minor memory blocks and output therefrom. Thus, even if the memory device has defective memory cells and has executed the exclusive operation of them, it is possible to effect an access without any time lag by the addition of a small amount of hardware.
REFERENCES:
patent: 3573751 (1971-04-01), DeLisle
patent: 3810301 (1974-05-01), Cook
patent: 3845476 (1974-10-01), Boehm
patent: 3882470 (1975-05-01), Hunter
patent: 3897626 (1975-08-01), Beausoleil
Fears Terrell W.
Nippon Telegraph and Telephone Public Corporation
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