Circuitry architecture and method for improving output tri-state

Details Circuitry architecture and method for improving output tri-state Circuitry architecture and method for improving output tri-state

1998-03-27

2000-02-22

Tokar, Michael

Electronic digital logic circuitry

Tri-state

With field-effect transistor

327374, H03K 1900, H03K 1902

Patent

active

06028448&

ABSTRACT:
An output buffer includes a differential data circuit for generating a first and a second differential signal, a pulse circuit for generating a pulse signal, a first latch circuit set by the first differential signal and reset by either the pulse signal or the second differential signal and a second latch circuit set by the second differential signal and reset by either the pulse signal or the first differential signal. An output circuit generates an output signal, the output signal being tri-stated whenever the pulse signal resets the first and second latch circuits. A method for improving output tri-state time of an output buffer includes the steps of pre-charging first and the second differential data inputs; tri-stating the buffer output upon each assertion of a timing signal; switching the output out of tri-state and into either a first or a second logic state only when one of the first and second differential data inputs changes to an active state; and returning to the pre-charging step. As the output of the buffer is tri-stated upon each assertion of the timing signal irrespective of whether a current cycle is a read, write cycle or de-select cycle, the switching time from one device connected to a bus to another device connected to the same bus is decreased.

REFERENCES:
patent: 5559465 (1996-09-01), Shah

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