Apparatus and method for caching lock conditions in a multi-proc

Details Apparatus and method for caching lock conditions in a multi-proc Apparatus and method for caching lock conditions in a multi-proc

1994-03-01

1999-12-21

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

711142, G06F 1308

Patent

active

060062991

ABSTRACT:
In a computer system, an apparatus for handling lock conditions wherein a first instruction executed by a first processor processes data that is common to a second processor while the second processor is locked from simultaneously executing a second instruction that also processes this same data. A lock bit is set when the first processor begins execution of the first instruction. Thereupon, the second processor is prevented from executing its instruction until the first processor has completed its processing of the shared data. Hence, the second processor queues its request in a buffer. The lock bit is cleared after the first processor has completed execution of its instruction. The first processor then checks the buffer for any outstanding requests. In response to the second processor's queued request, the first processor transmits a signal to the second processor indicating that the data is now not locked.

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"The Metaflow Architecture", pp. 10-13 and 63-73, by Val Popescu, Merle Schultz, John Spracklen, Gary Gibson, Bruce Lightner, and David Isaman, IEEE Micro, 1991.

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