Mask ROM device having highly integrated memory cell structure

Details Mask ROM device having highly integrated memory cell structure Mask ROM device having highly integrated memory cell structure

1992-04-23

1994-04-05

Ngo, Ngan

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257331, 257334, 257390, 257392, 257402, H01L 2702, H01L 2710, H01L 2715

Patent

active

053008049

ABSTRACT:
In a mask ROM device, a plurality of recesses extending parallel to each other are formed in a memory cell array region on the surface of a silicon substrate. In the direction intersecting the recesses, first and second transistor trains are formed in which select transistors and memory transistors are connected in series. The MOS transistors of the transistor trains have the sidewall of recess 5 formed as a channel region. A depletion implantation layer corresponding to data to be stored is formed on the sidewall of the recess. The first transistor train and the second transistor train are insulated and isolated from each other by an LOCOS isolation film.

REFERENCES:
patent: 4384345 (1983-05-01), Mikome
patent: 4630237 (1986-12-01), Miura et al.
A 4-Mb nand EEPROM with Tight Programmed V.sub.t, Distribuiton-IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991.

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