Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Capacitors

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36518905, 36518907, G11C 1124

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active

054327334

ABSTRACT:
A semiconductor memory device includes a memory cell array having a plurality of dynamic memory cells each of which has a plurality of cascade-connected MOS transistors and data storing capacitors each connected at one end to one end of a corresponding one of the MOS transistors, registers each provided for a corresponding one of columns of the memory cell array, for temporarily storing data time-sequentially read out from the memory cell; and switching elements for controlling the respective registers to be accessed independently from the memory cell array.

REFERENCES:
patent: 3763480 (1973-10-01), Weimer
patent: 4070590 (1978-01-01), Ieda
patent: 4225945 (1980-09-01), Kuo
patent: 4593382 (1986-06-01), Fujishima et al.
patent: 4648073 (1987-03-01), Kenney
patent: 4669063 (1987-05-01), Kirsch
patent: 4758987 (1988-07-01), Sakui
patent: 4943944 (1990-07-01), Sakui
patent: 4980863 (1990-12-01), Ogihara
patent: 5025294 (1991-06-01), Ema
patent: 5051954 (1991-09-01), Toda
patent: 5079746 (1992-01-01), Sato
patent: 5091761 (1992-02-01), Hiraiwa et al.
patent: 5091885 (1992-02-01), Ohsawa
patent: 5172198 (1992-12-01), Aritome
patent: 5184326 (1993-02-01), Hoffmann
Asakura et al., "Cell-Plate Line Connecting Complementary Bitline (C3) Architecture for Battery Operating DRAMs", 1991 Symposium on VLSI Circuits, May 30, 1991, pp. 59-60.
Kimura et al., "A Block-Oriented RAM with Half-Sized DRAM Cell and Quasi-Folded Data-line Architecture", ISCC 91, Slide Supplement, pp. 70-71.
Ohta et al., "Quadruply Self-Aligned Stacked High-Capacitance RAM Using Ta.sub.2 O.sub.3 High Density VLSI Dynamic Memory", IEEE Transactions on Electron Devices, vol. ED-29, No. 3, Mar. 1982, pp. 368-376.
Watanabe et al., "Stacked Capacitor Cells for High-density dynamic RAMs", IEDM Technical Digest, 1988, pp. 600-603.
Sunouchi et al., "A Surrounding Gate Transistor (SGT) Cell for 64/256Mbit DRAMs", IEDM Technical Digest, 1989, pp. 23-26.
Kimura, et al., "A Block-Oriented RAM with Half-Sized DRAM Cell and Quasi-Folded Data-Line Architecture," ISSCC 91, pp. 106-107, Feb. 14, 1991.
Shah et al., "A 4Mb DRAM with Cross-point Trench Transistor Cell", 1986 ISSCC Digest of Technical Papers, pp. 268-269.
Ema et al., "3-Dimensional Stacked Capacitor Cell For 16M and 64M DRAMs", 1988 IEDM Technical Digest, pp. 592-595.
Fujishima et al., "A Storage-Node-Boosted RAM with Word-Line Delay Compensation", IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, pp. 872-875, Oct. 1982.
Ohta et al., "A Novel Memory Cell Architecture for High-Density DRAMs", 1989 Symposium of VLSI Circuits, Digest of Tech. papers, pp. 101-102.
K. Arimoto et al., "A Circuit Design of Intelligent CDRAM With Automatic Write Back Capacity", 1990 Symp. on VLSI Circuits, Digest of Tech. Papers, pp. 79-80.

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