Control transfer indication in predecode which identifies contro

Electrical computers and digital processing systems: processing – Instruction alignment

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712206, 712207, 712213, 712217, G06F 9312

Patent

active

061346497

ABSTRACT:
A processor is configured to predecode instruction bytes prior to storing them in an instruction cache. The predecode information generated by the processor includes instruction boundary indications identifying which of the instruction bytes are boundaries of instructions and control transfer indications identifying which of the instructions are control transfer instructions. The combination of the control transfer indications and the instruction boundary indications allows the branch prediction mechanism to locate the branch instructions in a group of instruction bytes fetched from instruction cache by scanning the control transfer and instruction boundary indications. In one embodiment, the branch prediction mechanism attempts to predict up to two branch instructions per clock cycle. Accordingly, the branch prediction mechanism scans the control transfer and instruction boundary indications to locate the first two branch instructions within a group of instruction bytes fetched from the instruction cache. In one embodiment, the instruction boundary indications comprise a start bit corresponding to each instruction byte. The start bit is set if the corresponding instruction byte is the initial byte of an instruction, and clear if the corresponding instruction byte is not the initial byte of instruction. The control transfer indications may similarly comprise a control transfer bit corresponding to each instruction byte. If a byte is indicated to be the initial byte of an instruction via the start bit, the control transfer bit is used to indicate whether or not the instruction is a control transfer instruction.

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