Static information storage and retrieval – Addressing – Sync/clocking
Patent
1999-02-23
2000-10-17
Elms, Richard
Static information storage and retrieval
Addressing
Sync/clocking
3652335, 36523002, G11C 800
Patent
active
061341800
ABSTRACT:
A synchronous burst semiconductor memory device with a pipelined multi-bit prefetch architecture includes separate internal address generators for respective read and write burst modes. The synchronous memory device also adopts an auto-tracking bit line scheme to reduce core cycle time, a shortened main data line for current reduction, a noise immune circuit having high-speed transfer characteristics through a dual-rail reset dynamic circuit, and strobe clocks synchronized with the output data to guarantee processor data-validation time.
REFERENCES:
patent: 5499213 (1996-03-01), Niimi et al.
patent: 5812489 (1998-09-01), Matsui
patent: 5848431 (1998-12-01), Pawlowski
Kim Su-Chul
Park Hee-Choul
Elms Richard
Nguyen Tuan T.
Samsung Electronics Co,. Ltd.
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