Sensing circuit for a memory cell array

Details Sensing circuit for a memory cell array Sensing circuit for a memory cell array

1999-04-22

2000-10-17

Nelms, David

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365190, G11C 700

Patent

active

061341649

ABSTRACT:
The present invention addresses the foregoing need by providing a memory sensing circuit for accelerating a logic level transition of the complementary memory bit line of a complementary bit line pair having a full logic swing. The memory sensing circuit has a dual-rail circuit and at least one slew-rate acceleration circuit. The dual-rail circuit can be coupled across the complementary bit line pair for conditioning a signal undergoing a logical state transition placed on either of the bit lines. The at least one slew-rate acceleration circuit is coupled to the dual-rail circuit. The conditioned signal is input to the slew-rate acceleration circuit, said slew-rate acceleration circuit having an inverter circuit with an input terminal to receive the conditioned signal. A feed-back loop transistor, having a gate terminal coupled to an output terminal of the inverter circuit is responsive to an output signal placed on the output terminal such that the slew-rate of the conditioned signal is accelerated.

REFERENCES:
patent: 5504443 (1996-04-01), Gross et al.
patent: 5561630 (1996-10-01), Katoh et al.
patent: 5604705 (1997-02-01), Acklang et al.
patent: 5764589 (1998-06-01), Lofti

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