Method of making contact alignment for nonvolatile memory device

Details Method of making contact alignment for nonvolatile memory device Method of making contact alignment for nonvolatile memory device

1994-09-16

1995-09-05

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257382, 257388, 257755, 257900, H01L 2968

Patent

active

054480914

ABSTRACT:
A layout and fabrication technique for EPROMs and similar devices includes a preferred technique for partially self-aligning bit line contacts. In addition, a self-aligned, buried Vss line is provided which is in contact with the substrate for its entire length. This provides a highly conductive Vss line, allowing the size of such line to be diminished. The use of a buried Vss contact line and a partially self-aligned bit line contact contributes to a device layout having minimum cell sizes for a given feature size.

REFERENCES:
patent: 5233212 (1993-08-01), Ohi et al.
patent: 5235200 (1993-08-01), Komori et al.

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