Dynamic RAM

Details Dynamic RAM Dynamic RAM

1985-05-30

1987-06-30

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Data refresh

365230, G11C 700

Patent

active

046775927

ABSTRACT:
In a dynamic RAM, the refreshing operation is performed during one cycle of the read or write operation. A switch circuit selects either a row address signal output from address input circuit or a refresh row address signal output from a refresh circuit. By controlling the switch circuit by a switch selector, the refresh is performed during the operation delay time of the address input circuit or an input/output circuit for inputting and outputting data.

REFERENCES:
patent: 4079462 (1978-03-01), Koo
patent: 4333167 (1982-06-01), McElroy
patent: 4390972 (1983-06-01), Machida
Kawamoto, et al., "A 288Kb CMOS Pseudo SRAM", IEEE International Solid-State Circuits Conference, ISSCC, p. 276, (1984).

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