Stacked semiconductor chips

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip

Reexamination Certificate

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Details

C257S686000, C257SE25006

Reexamination Certificate

active

08076784

ABSTRACT:
Stacked semiconductor chips are disclosed. One embodiment provides a method including a first substrate having a first surface and an opposing second surface. The first substrate includes an array of first connection elements on the first surface of the first substrate. A second substrate has a first surface and an opposing second surface. The second substrate includes an array of second connection elements on the first surface of the second substrate. The first connection elements is attached to the second connection elements; and is thinning at least one of the first substrate and the second substrate after the attachment of the first connection elements to the second connection elements.

REFERENCES:
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patent: 6830956 (2004-12-01), Masumoto et al.
patent: 6872598 (2005-03-01), Liu
patent: 6984885 (2006-01-01), Harada et al.
patent: 7141487 (2006-11-01), Periasamy et al.
patent: 2003/0080410 (2003-05-01), Shibata
patent: 2003/0089973 (2003-05-01), Miyasaka
patent: 2004/0056344 (2004-03-01), Ogawa et al.
patent: 2006/0220261 (2006-10-01), Egawa
patent: 2007/0278657 (2007-12-01), Lee
patent: 2009/0065950 (2009-03-01), Lee et al.
patent: 2009/0149023 (2009-06-01), Koyanagi

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