Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-08-31
2011-12-27
Tabone, Jr., John J (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S764000, C714S768000, C714S718000, C714SE11034, C714S006240, C365S201000
Reexamination Certificate
active
08086936
ABSTRACT:
A memory system is provided that performs error correction at a memory device level that is transparent to a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises first error correction logic provided in write logic integrated in the memory hub device. The memory hub device comprises second error correction logic provided in read logic integrated in the memory hub device. The first error correction logic and the second error correction logic performs error correction operations on data transferred between a link interface and the set of memory devices. The memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code.
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Final Office Action mailed J
Gower Kevin C.
Maule Warren E.
Gerhardt Diana R.
International Business Machines - Corporation
Lammes Francis
Tabone, Jr. John J
Walder, Jr. Stephen J.
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