Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing
Reexamination Certificate
2006-02-13
2011-12-06
Jones, Hugh (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Timing
Reexamination Certificate
active
08073670
ABSTRACT:
A data row of delay time ratio coefficient (hereinafter referred to as DMAG value) is selected from a delay information library (D2) (S4) for every circuit cell in a use condition range of a logic circuit, and the minimum value or/and maximum value of a DMAG value is extracted (S5). The minimum value or/and the maximum delay time is/are calculated for every circuit cell by multiplying the standard delay time to the extracted DMAG value (S6). The above processing is performed for all the circuit cells constituting the logic circuit ((S7): NO), and the data set of the minimum or/and maximum delay time in the use condition range of the logic circuit is/are acquired for every circuit cell (S8). When the delay time characteristic of the circuit cell is nonlinear, the delay time serving as the minimum or/and the maximum for every circuit cell can be freely selected in the range of the circuit use condition unlike the case where the delay time is calculated by uniformly assigning the same use condition to all circuit cells.
REFERENCES:
patent: 5274568 (1993-12-01), Blinne et al.
patent: 5600568 (1997-02-01), Iwakura et al.
patent: 6389381 (2002-05-01), Isoda et al.
patent: 6718529 (2004-04-01), Iwanishi
patent: 6986115 (2006-01-01), Sakano
patent: 2004/0060021 (2004-03-01), Sakano
patent: 2004/0216067 (2004-10-01), Tanaka et al.
patent: 2005/0190702 (2005-09-01), Yamamoto et al.
patent: 9-311877 (1997-12-01), None
patent: 11-3366 (1999-01-01), None
patent: 2000-40098 (2000-02-01), None
patent: 2000-195960 (2000-07-01), None
Young-Hyun Jun, Ki Jun, Song-Bai Park, 1989, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions, vol. 8, Issue: 9, pp. 1027-1032.
Masao Inoue, et al., “Delay Parameter Extracting System on Standard Cell”, Information Processing Society of Japan, vol. 33, No. 3, pp. 2251-2252, Oct. 23, 1986.
Toru Toyoda, et al., “A VLSI Delay Library Generation Aid System”, Information Processing Society of Japan, vol. 91, No. 58, pp. 1-8, Jul. 12, 1991.
Toru Toyoda, et al., “ASIC Library Generation System”, NEC Technical Journal, vol. 47, No. 3, pp. 170-173, Mar. 25, 1994.
Masao Inoue, et al., “Delay Parameter Extracting System on Standard Cell”, Information Processing Society of Japan, vol. 33, No. 3, pp. 2251-2252, Oct. 23, 1986.
Toru Toyoda, et al., “ASIC Library Generation System”, NEC Technical Journal, vol. 47, No. 3, pp. 170-173, Mar. 25, 1994.
Fujitsu Semiconductor Limited
Jones Hugh
Staas & Halsey , LLP
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