Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

2009-02-03

2011-12-27

Smith, Zandra (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S199000, C257S374000, C257SE21576, C257SE21633, C257SE21635

Reexamination Certificate

active

08084826

ABSTRACT:
An element larger than silicon is ion-implanted to a contact liner in an N-channel region to break constituent atoms of the contact liner in the N-channel region. An element larger than silicon is ion-implanted to the contact liner in a P-channel region to break constituent atoms of the contact liner, oxygen or the like is ion-implanted. Thereafter, heat treatment is performed to cause shrinkage of the contact liner in the N-channel region to form an n-channel contact liner, and to cause expansion of the contact liner in the P-channel region to form a p-channel contact liner.

REFERENCES:
patent: 6573172 (2003-06-01), En et al.
patent: 2005/0285187 (2005-12-01), Bryant et al.
patent: 2006/0157795 (2006-07-01), Chen et al.
patent: 2006/0202278 (2006-09-01), Shima et al.
patent: 2007/0296027 (2007-12-01), Yang et al.
patent: 2008/0064173 (2008-03-01), Hung
C. D. Sheraw et al., “Dual Stress Liner Enhancement in Hybrid Orientation Technology,” (2-1), 2005 Symposium on VSLI Technology Digest of Technical Papers, pp. 12-13.
D.V. Singh et al., “Stress Memorization in High-Performance FDSOI Devices with Ultra-Thin Silicon Channels and 25nm Gate Lengths,” IEDM 2005.

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