Semiconductor memory device having DRAM-compatible...

Static information storage and retrieval – Systems using particular element – Resistive

Reexamination Certificate

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C365S203000, C365S205000, C365S230030

Reexamination Certificate

active

08072794

ABSTRACT:
In synchronism with an active command, a row address and a column address are simultaneously received, and a page address is received in synchronism with a read command or a write command. Word drivers select a word line based on the row address, and column switches select a bit line based on the column address. A page address decoder selects any one of read/write amplifiers corresponding to each page based on the page address. With this configuration, a specification for a DRAM such as an access cycle can be satisfied without arranging an amplifier for each bit line, and thus it becomes possible to secure a compatibility with a DRAM while reducing a chip area.

REFERENCES:
patent: 7154788 (2006-12-01), Takemura et al.
patent: 7643334 (2010-01-01), Lee et al.
patent: 2006/0013058 (2006-01-01), Kang et al.
patent: 2008/0074931 (2008-03-01), Kim et al.
patent: 2009/0027953 (2009-01-01), Kang et al.
patent: 2009/0235014 (2009-09-01), Yim et al.
patent: 2010/0027329 (2010-02-01), Lee et al.
patent: 2005-158199 (2005-06-01), None

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