Timer circuit and timer method

Details Timer circuit and timer method Timer circuit and timer method

2010-07-02

2011-12-27

Baderman, Scott (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S038100, C713S002000

Reexamination Certificate

active

08086901

ABSTRACT:
A timer circuit and a timer method are provided for a BIOS of an electronic device. The timer circuit includes a processing module, a setting module, and a display module. The processing module includes a microprocessor unit (MCU), a clock circuit20, and a reset circuit. The timer circuit electronically connects with a debug card to measure a running time of a procedure of the BIOS of the electronic device. A timer result of the measurement is displayed on the display module.

REFERENCES:
patent: 2004/0153811 (2004-08-01), Kuo
patent: 2004/0153812 (2004-08-01), Miyayama et al.
patent: 2004/0164990 (2004-08-01), Chan et al.
patent: 2005/0102579 (2005-05-01), Miyayama et al.
patent: 2005/0257199 (2005-11-01), Johansson et al.
patent: 2006/0259826 (2006-11-01), Swoboda et al.
patent: 2007/0234122 (2007-10-01), Lu
patent: 2008/0010516 (2008-01-01), Lu
patent: 2008/0141073 (2008-06-01), Shih et al.
patent: 2008/0163001 (2008-07-01), Ko et al.
patent: 2008/0201572 (2008-08-01), Shih
patent: 2009/0240934 (2009-09-01), Chou
patent: 2010/0318707 (2010-12-01), Tanaka et al.
patent: 2011/0091039 (2011-04-01), Spitz et al.
patent: 249099 (2006-02-01), None

Affiliated with

Also associated with

Rating

Timer circuit and timer method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Timer circuit and timer method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timer circuit and timer method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4307211