Semiconductor chip package, stacked package comprising...

Details Semiconductor chip package, stacked package comprising... Semiconductor chip package, stacked package comprising...

2009-07-24

2011-12-27

Dickey, Thomas L (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With semiconductor element forming part

C257SE25027, C257SE23141

Reexamination Certificate

active

08084850

ABSTRACT:
According to an example embodiment, a semiconductor chip package includes a substrate comprising a substrate body having a first main surface, a second main surface, and a cavity that defines an opening in the first main surface, and a layer of electrically conductive material integral with the substrate body. The layer of electrically conductive material constitutes an interconnection pattern of the substrate. The semiconductor chip packages further includes a semiconductor chip disposed within the cavity and mounted to the substrate. The chip includes electrical contacts in the form of pads and the pads face in a direction towards the bottom of the cavity such that the chip has a flip-chip orientation with respect to the substrate. The pads are electrically conductively bonded to respective portions of the interconnection pattern.

REFERENCES:
patent: 5397917 (1995-03-01), Ommen et al.
patent: 5600541 (1997-02-01), Bone et al.
patent: 6084297 (2000-07-01), Brooks et al.
patent: 2004/0090756 (2004-05-01), Ho et al.
patent: 2007/0069371 (2007-03-01), Iksan et al.
patent: 2004-247706 (2004-09-01), None
patent: 100677184 (2007-01-01), None

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