Method and layout of semiconductor device with reduced...

Details Method and layout of semiconductor device with reduced... Method and layout of semiconductor device with reduced...

2007-07-26

2011-10-11

Tran, Tan N (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S336000, C257S389000, C257SE21598

Reexamination Certificate

active

08035140

ABSTRACT:
An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.

REFERENCES:
patent: 7084462 (2006-08-01), Warnock et al.
patent: 7119399 (2006-10-01), Ma et al.
patent: 2002/0145172 (2002-10-01), Fujishima et al.
patent: 2005/0253175 (2005-11-01), Taddiken
patent: 2007/0034942 (2007-02-01), Xu et al.
patent: 2007/0034986 (2007-02-01), Hokomoto et al.
patent: 2007/0228497 (2007-10-01), Shimizu
patent: 102 50 832 (2004-05-01), None

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