Semiconductor memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S316000, C257S306000, C257S390000, C257SE27103, C257SE29309

Reexamination Certificate

active

08030700

ABSTRACT:
A semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate and having a plurality of insulator layers and a plurality of conductive layers alternately stacked; a semiconductor layer provided inside a through-hole formed so as to pass through the stacked body and extending in a stacking direction of the insulator layers and the conductive layers; and a charge trap layer provided between the conductive layer and the semiconductor layer. A lower part in the semiconductor layer is narrower than an upper part therein, and at least the lowermost layer in the conductive layers is thinner than the uppermost layer therein.

REFERENCES:
patent: 2002/0195668 (2002-12-01), Endoh et al.
patent: 2007/0158736 (2007-07-01), Arai et al.
patent: 2007/0252201 (2007-11-01), Kito et al.
patent: 2008/0048245 (2008-02-01), Kito et al.
patent: 2008/0073635 (2008-03-01), Kiyotoshi et al.
patent: 2008/0093664 (2008-04-01), Yun et al.
patent: 2008/0128780 (2008-06-01), Nishihara et al.
patent: 2008/0149992 (2008-06-01), Gidon
patent: 2008/0173928 (2008-07-01), Arai et al.
patent: 2007-266143 (2007-10-01), None
H. Tanaka et al.,“Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, 2007 Symposium on VLSI Technology Digest of Technical Papers, 1 page.
Yoshiaki Fukuzumi et al., “Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory”, IEDM Tech. Digest, 2007, 4 pages.

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