Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2010-10-07
2011-10-11
Mai, Son (Department: 2827)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S154000
Reexamination Certificate
active
08036023
ABSTRACT:
A circuit and method are provided in which a six-transistor (6-T) SRAM memory cell is hardened to single-event upsets by adding isolation-field effect transistors (“iso-fets”) connected between the reference voltage Vdd and the field-effect transistors (“fets”) respectively corresponding to first and second inverters of the memory cell. According to certain embodiments, the control gates of first and second P-iso-fets are respectively tied to the control gates of first and second pull-up P-fets. According to certain embodiments, first and second N-iso-fets are connected between the output nodes of the memory cell and the pull-down N-fets respectively corresponding to the first and second inverters. The control gates of the first and second N-iso-fets are respectively tied to the control gates of the first and second pull-down N-fets. Again according to certain embodiments, one or more of the iso-fets are physically removed from the proximity of other transistors which comprise the memory cell.
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Haddad Nadim F.
Lawrence Reed K.
BAE Systems Information and Electronic Systems Integration Inc.
Graybeal Jackson Haley
Long Daniel J.
Mai Son
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