Main spacer trim-back method for replacement gate process

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C257SE21199, C257SE21296, C257SE21438, C438S744000, C438S745000, C438S791000

Reexamination Certificate

active

08039388

ABSTRACT:
The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.

REFERENCES:
patent: 6821713 (2004-11-01), Holbrook et al.
patent: 2005/0186747 (2005-08-01), Amos et al.
patent: 2007/0241378 (2007-10-01), Aritome
patent: 2008/0206973 (2008-08-01), Johnson et al.
patent: 2008/0303060 (2008-12-01), Han et al.

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