Method and apparatus for controlling memory precharge operation

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

Reexamination Certificate

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C711S105000, C711SE12001

Reexamination Certificate

active

08069303

ABSTRACT:
A memory controller sequentially holds access requests including access addresses. A semiconductor memory includes a plurality of banks each having a plurality of pages. The memory controller decides page hit/page miss of the bank corresponding to each of the held access addresses. Further, the memory controller outputs an all-banks precharge command for performing a precharge operation of all the banks when deciding, based on an analysis of the successive access addresses, that outputting the all-banks precharge command results in improvement in access efficiency. It is possible to precharge the plural banks only by supplying the all-banks precharge command once, and therefore, in a case where the number of empty cycles for the insertion of a command is small, it is possible to supply the command efficiently to the semiconductor memory according to the states of the banks.

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patent: 2005/0071536 (2005-03-01), Osborne
patent: 2008/0091890 (2008-04-01), Shrader et al.
patent: 2009/0292886 (2009-11-01), Shrader et al.
patent: 9-237490 (1997-09-01), None
patent: 2002-342159 (2002-11-01), None

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