Semiconductor device with stressed fin sections, and related...

Details Semiconductor device with stressed fin sections, and related... Semiconductor device with stressed fin sections, and related...

2009-10-09

2011-10-04

Luu, Chuong A. (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S283000, C438S176000, C438S587000

Reexamination Certificate

active

08030144

ABSTRACT:
A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

REFERENCES:
patent: 2006/0022268 (2006-02-01), Oh et al.
patent: 2006/0220131 (2006-10-01), Kinoshita et al.

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